The demand for flexible and easily reconfigurable receivers along with the relatively recent emergence of low cost, high speed, integrated circuit technology has lead to the increasing popularity of a broad class of radio receivers employing direct radio frequency (RF) to baseband sampling. Examples of these radio receivers may be found in communications as well as instrumentation (i.e., oscilloscopes, spectrum analyzers, or the like) systems.
While IF (intermediate frequency) sampling receivers are used to down-convert a received signal to an intermediate frequency, these types of architectures are not particularly suitable for low cost, low power, high fidelity, flexible commercial communications systems that receive GHz RF signals. RF sampling systems that employ time interleaved data converters are more suitable for low power, high fidelity GHz RF applications.
Even though time interleaving makes possible the efficient implementation of high resolution and high rate sampling systems, it does not improve clock jitter immunity. Clock jitter has a very deleterious impact on sampling systems. Clock jitter manifests as noise at the output of a sampler and therefore may degrade the signal to noise ratio (SNR) performance delivered by the sampler. When sampling high frequency (GHz RF) signals, the clock jitter performance required for high resolution sampling receiver systems may be impractical for low cost, low power commercial communications applications.
While some systems do deliver improved clock jitter immunity, they are not particularly flexible or necessarily power efficient. Therefore, there is a need for sampling systems that delivers improved clock jitter immunity with increased flexibility.